TY - GEN
T1 - Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications
AU - Deng, Shan
AU - Benkhelifa, Mahdi
AU - Thomann, Simon
AU - Faris, Zubair
AU - Zhao, Zijian
AU - Huang, Tzu Jung
AU - Xu, Yixin
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
AU - Amrouch, Hussam
N1 - Funding Information:
With a compact implementation of 3-input MAJ of XNOR gate, it can be used for the acceleration of BNN. Though BNN greatly simplifies the multiplication into simple XNOR gate when restricting the input and weight to be binary. However, for BNN with a large model size (Fig.2(d)), the adder tree exponentially grows and becomes a bottleneck. To address the issue, we approximate the 1-bit full adder (used in the entire first layer of the adder tree) with a MAJ gate (Fig.11(a)), as in [11], which together with the XNOR gate can be replaced with a compact MAJ of XNOR gate using our FE multi-gate structure. In this way, significant area saving (up to 21x reduction) is achieved as shown in the number of transistors needed to implement a 3-input XNOR and accumulation computation (Fig.11(b)). This area saving comes with only 2% accuracy loss when evaluating the Fashion MNIST dataset using the VGG-based BNN (Fig.11(c)). In addition, the energy-latency plot for the execution of compact gate shows that even excluding the memory access, our FE MAJ of XNOR approach shows a comparable energy-delay product as the CMOS implementation. All these results demonstrate great promise of our approach. Note that, the proposed device structure can also benefit from the vertical 3D structure and maximize its density. IV. CONCLUSIONS In this work, we propose a compact and novel ferroelectric programmable majority gate that can accelerate BNN inference. Through comprehensive theoretical and experimental investigations, the logic functionality of majority of AND operation between the gate input and polarization configuration is validated. Building on this, we implemented and validated the functionality of the majority of XNOR gate and shown significant area saving and memory access elimination when replacing the XNOR and adder tree in CMOS implementations of binary neural network. There the programmable majority gate is highly promising for compute-in-memory applications. Acknowledgement: Authors thank O. Prakahs, A. Mema, A. Dave, F. Frustaci, M. Yayla for their help in BNN implementation/evaluation and S. Chatterjee for TCAD simulation. This work was primarily supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences Energy Frontier Research Centers program under Award Number DE-SC0021118 and partially supported by Army Research Office under Grant Number W911NF-21-1-0341 and NSF 2008365 and NSF 2132918. REFERENCES: [1] P. Wang et al., IEEE TVLSI 2019; [2] F. Wang et al., IEEE EDL 2020; [3] J. Hwang et al., IEEE EDL 2022; [4] S. Ogasawara et al., Jpn. J. Appl. Phys. 2002; [5] G. Lee et al., IEEE EDL 2022; [6] T. Shibata et al., IEEE TED 1992; [7] Q. Liu et al., IEDM 2013; [8] K. Ni et al., IEDM 2021; [9] K. Ni et al., IEDM 2018; [10] R. Seyedramin et al., ICFPT 2019.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In this work, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.
AB - In this work, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.
UR - http://www.scopus.com/inward/record.url?scp=85147524356&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85147524356&partnerID=8YFLogxK
U2 - 10.1109/IEDM45625.2022.10019400
DO - 10.1109/IEDM45625.2022.10019400
M3 - Conference contribution
AN - SCOPUS:85147524356
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 3671
EP - 3674
BT - 2022 International Electron Devices Meeting, IEDM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 International Electron Devices Meeting, IEDM 2022
Y2 - 3 December 2022 through 7 December 2022
ER -