Comparator generation and selection for highly linear CMOS flash analog-to-digital converter

This paper presents a comparator generation and selection method to reduce the linearity errors - DNL and INL - for a CMOS flash analog-to-digital converter (ADC) based on threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires 2ⁿ - 1 comparators like conventional flash ADCs. However, each comparator in the TIQ flash ADC has different sizes to provide internal reference voltages, while the differential comparators have identical sizes. The design method has been incorporated into a software package and the 2ⁿ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The linearity errors against the CMOS process, power supply voltage, and temperature variations are significantly improved by the proposed comparator generation and selection method for the TIQ flash ADC. Especially, the DNL dependence on the CMOS process variation can be almost eliminated. The simulation results show 82.6% of DNL and 32.5% of INL improvements against CMOS process variation. For the other variations - power supply voltage and temperature - 43.5% for DNL and 6.0% for INL improvement has been achieved. The prototype chips have been fabricated and the chip test results confirms the simulation results.