Comparison of four two-dimensional gate matrix layout tools

A comparison of four layout tools is presented. The layout style is a two-dimensional gate matrix. The first layout tool discussed uses standard simulated annealing. Annealing on gate clusters instead of individual gates can be used to improve the layout results. Two different ways of determining good gate clusters for use in the annealing process are compared. The first way uses clusters derived from user-specified gate hierarchies, while the second determines clusters based on gate connectivity. The fourth layout tool uses a decomposition scheme based on quadrisection. Layout results for a set of benchmark circuits are presented for each of the tools. It is clear from the results that standard simulated annealing should not be used. Some form of clustering, either using composition, as is done in designer and parser generated clusters, or using decomposition, as is done in cubist, should be used. With such clustering, transistor density is more dependent on circuit regularity than on circuit size. Of the two composition-based cluster approaches, the scheme using parser outperformed designer-specified clusters. For structured circuits both designer-specified and parser-generated clusters did better than quadrisection, while for less structured circuits only parser-generated clusters gave higher transistor densities than quadrisection.