TY - GEN
T1 - Comparison of two digit serial VLSI adders
AU - Irwin, Mary Jane
AU - Owens, Robert Michael
PY - 1988/12/1
Y1 - 1988/12/1
N2 - The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level description suitable for static CMOS implementation for one of the adders is given. This gate-level description can be input to a layout tool to automatically produce the CMOS gate matrix layout of the description. Finally, word-parallel adders built out of the two digit serial adders are discussed and compared.
AB - The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level description suitable for static CMOS implementation for one of the adders is given. This gate-level description can be input to a layout tool to automatically produce the CMOS gate matrix layout of the description. Finally, word-parallel adders built out of the two digit serial adders are discussed and compared.
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M3 - Conference contribution
AN - SCOPUS:0024131348
SN - 0818608722
T3 - 1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc
SP - 227
EP - 229
BT - 1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc
PB - Publ by IEEE
ER -