Compiler-directed instruction cache leakage optimization

W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

66 Scopus citations


Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.

Original languageEnglish (US)
Title of host publicationProceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002
PublisherIEEE Computer Society
Number of pages11
ISBN (Electronic)0769518591
StatePublished - 2002
Event35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002 - Istanbul, Turkey
Duration: Nov 18 2002Nov 22 2002

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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