Compiler-guided leakage optimization for banked scratch-pad memories

M. Kandemir; M. J. Irwin; G. Chen; I. Kolcu

doi:10.1109/TVLSI.2005.859478

Compiler-guided leakage optimization for banked scratch-pad memories

M. Kandemir
, M. J. Irwin
, G. Chen
, I. Kolcu

Research output: Contribution to journal › Article › peer-review

39 Scopus citations

Abstract

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.

Original language	English (US)
Pages (from-to)	1136-1146
Number of pages	11
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	13
Issue number	10
DOIs	https://doi.org/10.1109/TVLSI.2005.859478
State	Published - Oct 2005

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2005.859478

Cite this

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title = "Compiler-guided leakage optimization for banked scratch-pad memories",

abstract = "Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.",

author = "M. Kandemir and Irwin, \{M. J.\} and G. Chen and I. Kolcu",

note = "Funding Information: Manuscript received October 22, 2004; revised August 25, 2005. This work was supported in part by the National Science Foundation under CAREER Award 0093082 and by a grant from GSRC. M. Kandemir, M. J. Irwin, and G. Chen are with the Computer Science and Engineering Department, The Pennsylvania State University, University Park, PA 16802 USA (e-mail: [email protected]). I. Kolcu is with the Computation Department, University of Manchester, Manchester M60 1QD, U.K. (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2005.859478",

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doi = "10.1109/TVLSI.2005.859478",

language = "English (US)",

volume = "13",

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AU - Irwin, M. J.

AU - Chen, G.

AU - Kolcu, I.

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N2 - Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.

AB - Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.

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Compiler-guided leakage optimization for banked scratch-pad memories

Abstract

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