TY - JOUR
T1 - Compiler-guided leakage optimization for banked scratch-pad memories
AU - Kandemir, M.
AU - Irwin, M. J.
AU - Chen, G.
AU - Kolcu, I.
N1 - Funding Information:
Manuscript received October 22, 2004; revised August 25, 2005. This work was supported in part by the National Science Foundation under CAREER Award 0093082 and by a grant from GSRC. M. Kandemir, M. J. Irwin, and G. Chen are with the Computer Science and Engineering Department, The Pennsylvania State University, University Park, PA 16802 USA (e-mail: [email protected]). I. Kolcu is with the Computation Department, University of Manchester, Manchester M60 1QD, U.K. (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2005.859478
PY - 2005/10
Y1 - 2005/10
N2 - Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
AB - Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
UR - https://www.scopus.com/pages/publications/31144441199
UR - https://www.scopus.com/pages/publications/31144441199#tab=citedBy
U2 - 10.1109/TVLSI.2005.859478
DO - 10.1109/TVLSI.2005.859478
M3 - Article
AN - SCOPUS:31144441199
SN - 1063-8210
VL - 13
SP - 1136
EP - 1146
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 10
ER -
