Compiler support for block buffering

M. Kandemir, J. Ramanujam, U. Sezer

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


On-chip caches consume a significant fraction of energy in current microprocessors. Hence, hardware techniques such as block buffering have been developed and shown to be effective in reducing on-chip cache energy consumption. We are not aware of any software solutions to exploit block buffering. This paper presents a compiler-based approach that modifies both code and variable layout to effectively exploit block buffering, and is aimed at the class of embedded codes that make heavy use of scalar variables. Unlike previous work that uses only storage pattern optimization, our solution integrates both code restructuring and storage pattern optimization. Experimental results on a set of complete programs demonstrate that our solution leads to significant energy savings.

Original languageEnglish (US)
Number of pages4
StatePublished - 2001
EventInternational Symposium on Low Electronics and Design (ISLPED'01) - Huntington Beach, CA, United States
Duration: Aug 6 2001Aug 7 2001


OtherInternational Symposium on Low Electronics and Design (ISLPED'01)
Country/TerritoryUnited States
CityHuntington Beach, CA

All Science Journal Classification (ASJC) codes

  • General Engineering


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