Compound semiconductor based tunnel transistor logic

Suman Datta, S. Mookerjea, D. Mohata, L. Liu, V. Saripalli, V. Narayanan, T. Mayer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this invited talk, we introduce a new transistor architecture based on inter-band tunneling mechanism as a step towards exploring steep switching transistors for energy efficient logic applications. While others have researched on developing these transistors in the Si, Ge and their alloys, we have focused specifically on narrow gap compound semiconductor (CS) systems to develop tunnel transistors. We address the following topics regarding the CS-based tunnel transistor architecture: a) the choice of appropriate materials to tune the transfer characteristics over a specified gate voltage swing b) the characteristic screening lengths in these device essential for scaling, c) an effective way to estimate the switching speed of tunnel transistors, d) digital circuit design methodologies utilizing tunnel transistors.

Original languageEnglish (US)
Title of host publication2010 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2010
StatePublished - Dec 1 2010
Event2010 International Conference on Compound Semiconductor Manufacturing Technology - Portland, OR, United States
Duration: May 17 2010May 20 2010

Publication series

Name2010 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2010

Other

Other2010 International Conference on Compound Semiconductor Manufacturing Technology
Country/TerritoryUnited States
CityPortland, OR
Period5/17/105/20/10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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