Constraint-based code mapping for heterogeneous chip multiprocessors

S. Tosun, N. Mansouri, M. Kandemir, O. Ozturk

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Number of pages2
StatePublished - Dec 1 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: Sep 25 2005Sep 28 2005

Publication series

NameProceedings - IEEE International SOC Conference


Other2005 IEEE International SOC Conference
Country/TerritoryUnited States
CityHerndon, VA

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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