TY - GEN
T1 - Constraint-based code mapping for heterogeneous chip multiprocessors
AU - Tosun, S.
AU - Mansouri, N.
AU - Kandemir, M.
AU - Ozturk, O.
PY - 2005/12/1
Y1 - 2005/12/1
N2 - Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.
AB - Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.
UR - http://www.scopus.com/inward/record.url?scp=30844464120&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=30844464120&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:30844464120
SN - 0780392647
T3 - Proceedings - IEEE International SOC Conference
SP - 89
EP - 90
BT - Proceedings - IEEE International SOC Conference, 2005 SOCC
A2 - Ha, D.
A2 - Krishnamurthy, R.
A2 - Kim, S.
A2 - Marshall, A.
T2 - 2005 IEEE International SOC Conference
Y2 - 25 September 2005 through 28 September 2005
ER -
