Constraint-based code mapping for heterogeneous chip multiprocessors

S. Tosun; N. Mansouri; M. Kandemir; O. Ozturk

Constraint-based code mapping for heterogeneous chip multiprocessors

S. Tosun
, N. Mansouri
, M. Kandemir
, O. Ozturk

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference, 2005 SOCC
Editors	D. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages	89-90
Number of pages	2
State	Published - 2005
Event	2005 IEEE International SOC Conference - Herndon, VA, United States Duration: Sep 25 2005 → Sep 28 2005

Publication series

Name	Proceedings - IEEE International SOC Conference

Other

Other	2005 IEEE International SOC Conference
Country/Territory	United States
City	Herndon, VA
Period	9/25/05 → 9/28/05

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{e8471188ae9649389075a42fc499f068,

title = "Constraint-based code mapping for heterogeneous chip multiprocessors",

abstract = "Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.",

author = "S. Tosun and N. Mansouri and M. Kandemir and O. Ozturk",

year = "2005",

language = "English (US)",

isbn = "0780392647",

series = "Proceedings - IEEE International SOC Conference",

pages = "89--90",

editor = "D. Ha and R. Krishnamurthy and S. Kim and A. Marshall",

booktitle = "Proceedings - IEEE International SOC Conference, 2005 SOCC",

note = "2005 IEEE International SOC Conference ; Conference date: 25-09-2005 Through 28-09-2005",

}

Tosun, S, Mansouri, N, Kandemir, M & Ozturk, O 2005, Constraint-based code mapping for heterogeneous chip multiprocessors. in D Ha, R Krishnamurthy, S Kim & A Marshall (eds), Proceedings - IEEE International SOC Conference, 2005 SOCC., P.7, Proceedings - IEEE International SOC Conference, pp. 89-90, 2005 IEEE International SOC Conference, Herndon, VA, United States, 9/25/05.

Constraint-based code mapping for heterogeneous chip multiprocessors. / Tosun, S.; Mansouri, N.; Kandemir, M. et al.
Proceedings - IEEE International SOC Conference, 2005 SOCC. ed. / D. Ha; R. Krishnamurthy; S. Kim; A. Marshall. 2005. p. 89-90 P.7 (Proceedings - IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Constraint-based code mapping for heterogeneous chip multiprocessors

AU - Tosun, S.

AU - Mansouri, N.

AU - Kandemir, M.

AU - Ozturk, O.

PY - 2005

Y1 - 2005

N2 - Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.

AB - Mapping a real-time embedded application onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an ILP (Integer Linear Programming) based framework that maps a given application (represented as a task graph) onto an HCM (Heterogeneous Chip Multiprocessor) architecture. Our framework can be used with several objective functions such as energy, performance, and fallibility (opposite of reliability). We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to minimize fallibility.

UR - https://www.scopus.com/pages/publications/30844464120

UR - https://www.scopus.com/pages/publications/30844464120#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:30844464120

SN - 0780392647

T3 - Proceedings - IEEE International SOC Conference

SP - 89

EP - 90

BT - Proceedings - IEEE International SOC Conference, 2005 SOCC

A2 - Ha, D.

A2 - Krishnamurthy, R.

A2 - Kim, S.

A2 - Marshall, A.

T2 - 2005 IEEE International SOC Conference

Y2 - 25 September 2005 through 28 September 2005

ER -

Constraint-based code mapping for heterogeneous chip multiprocessors

Abstract

Publication series

Other

UN SDGs

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this