Even though Moore's Law continues to provide increasing transistor counts, the rise of the utilization wall limits the number of transistors that can be powered on and results in a large region of dark silicon. Prior studies have proposed energy-efficient core designs to address the 'dark silico' problem. Nevertheless, the research for addressing dark silicon challenges in uncore components, such as shared cache, on-chIP interconnect, etc, that contribute significant on-chIP power consumption is largely unexplored. In this paper, we first illustrate that the power consumption of uncore components cannot be ignored to meet the chIP's power constraint. We then introduce techniques to design energy-efficient uncore components, including shared cache and on-chIP interconnect. The design challenges and opportunities to exploit 3D techniques and non-volatile memory (NVM) in dark-silicon-aware architecture are also discussed.