TY - GEN
T1 - Correlation of PDN impedance with jitter and voltage margin for high speedchannels
AU - Laddha, Vishal
AU - Swaminathan, Madhavan
PY - 2008
Y1 - 2008
N2 - Timing margin (jitter) and voltage margin (noise) are the main bottlenecks in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities such as signal via transitions and plane cutouts is a major source of jitter and noise introduced by the package and the printed circuit boards on the signal interconnects of these channels. In this paper, we present a new methodology to correlate SSN induced signal jitter and noise with the power distribution network (PDN) impedance by studying the exact mechanism of how the PDN impedance affects signal jitter and voltage margin. Further, we validate the analysis by both simulations and measurements and suggest design practices to reduce jitter and noise on the signal.
AB - Timing margin (jitter) and voltage margin (noise) are the main bottlenecks in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities such as signal via transitions and plane cutouts is a major source of jitter and noise introduced by the package and the printed circuit boards on the signal interconnects of these channels. In this paper, we present a new methodology to correlate SSN induced signal jitter and noise with the power distribution network (PDN) impedance by studying the exact mechanism of how the PDN impedance affects signal jitter and voltage margin. Further, we validate the analysis by both simulations and measurements and suggest design practices to reduce jitter and noise on the signal.
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U2 - 10.1109/EPEP.2008.4675880
DO - 10.1109/EPEP.2008.4675880
M3 - Conference contribution
AN - SCOPUS:58049124944
SN - 9781424428731
T3 - Electrical Performance of Electronic Packaging, EPEP
SP - 73
EP - 76
BT - Electrical Performance of Electronic Packaging, EPEP 2008
T2 - 17th Conference on Electrical Performance of Electronic Packaging, EPEP 2008
Y2 - 27 October 2008 through 29 October 2008
ER -