Correlation of PDN impedance with jitter and voltage margin for high speedchannels

Vishal Laddha, Madhavan Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Timing margin (jitter) and voltage margin (noise) are the main bottlenecks in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities such as signal via transitions and plane cutouts is a major source of jitter and noise introduced by the package and the printed circuit boards on the signal interconnects of these channels. In this paper, we present a new methodology to correlate SSN induced signal jitter and noise with the power distribution network (PDN) impedance by studying the exact mechanism of how the PDN impedance affects signal jitter and voltage margin. Further, we validate the analysis by both simulations and measurements and suggest design practices to reduce jitter and noise on the signal.

Original languageEnglish (US)
Title of host publicationElectrical Performance of Electronic Packaging, EPEP 2008
Pages73-76
Number of pages4
DOIs
StatePublished - 2008
Event17th Conference on Electrical Performance of Electronic Packaging, EPEP 2008 - San Jose, CA, United States
Duration: Oct 27 2008Oct 29 2008

Publication series

NameElectrical Performance of Electronic Packaging, EPEP

Conference

Conference17th Conference on Electrical Performance of Electronic Packaging, EPEP 2008
Country/TerritoryUnited States
CitySan Jose, CA
Period10/27/0810/29/08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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