TY - GEN
T1 - Coupling noise analysis and high frequency design optimization of power/ground plane stack-up in embedded chip substrate cavities
AU - Sankaran, Nithya
AU - Ramdas, Venkatesh Chelukka
AU - Lee, Baik Woo
AU - Sundaram, Venky
AU - Engin, Ege
AU - Iyer, Mahadevan
AU - Swaminathan, Madhavan
AU - Tummala, Rao
PY - 2008
Y1 - 2008
N2 - Future electronic systems demand faster, smaller, lighter and thinner products. Embedding Active and Passive components in package size boards is one of the major steps in accomplishing system level miniaturization and multifunctionality. All multifunctional system packages should pay attention to Signal and Power integrity for ensuring proper operation of the system. Predominant challenge encountered with respect to power integrity in mixed signal systems is coupling through the power distribution network. This coupling which is a form of noise affects power integrity if left unchecked, especially in case of embedded actives where there are large apertures (die sized) in the metal planes and cavities in dielectric to accommodate the chips. This paper for the first time brings out coupling noise analysis for different power/ground plane stack-ups in embedded chip substrate cavities.
AB - Future electronic systems demand faster, smaller, lighter and thinner products. Embedding Active and Passive components in package size boards is one of the major steps in accomplishing system level miniaturization and multifunctionality. All multifunctional system packages should pay attention to Signal and Power integrity for ensuring proper operation of the system. Predominant challenge encountered with respect to power integrity in mixed signal systems is coupling through the power distribution network. This coupling which is a form of noise affects power integrity if left unchecked, especially in case of embedded actives where there are large apertures (die sized) in the metal planes and cavities in dielectric to accommodate the chips. This paper for the first time brings out coupling noise analysis for different power/ground plane stack-ups in embedded chip substrate cavities.
UR - https://www.scopus.com/pages/publications/51349150844
UR - https://www.scopus.com/pages/publications/51349150844#tab=citedBy
U2 - 10.1109/ECTC.2008.4550237
DO - 10.1109/ECTC.2008.4550237
M3 - Conference contribution
AN - SCOPUS:51349150844
SN - 9781424422302
T3 - Proceedings - Electronic Components and Technology Conference
SP - 1874
EP - 1879
BT - 2008 Proceedings 58th Electronic Components and Technology Conference, ECTC
T2 - 2008 58th Electronic Components and Technology Conference, ECTC
Y2 - 27 May 2008 through 30 May 2008
ER -