TY - GEN
T1 - Cross-Layer Optimizations for Ferroelectric Neuromorphic Computing
AU - M Nafiul Islam, A. N.
AU - Ni, Kai
AU - Sengupta, Abhronil
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Hardware paradigms for neuromorphic computing mimic the functionalities of brain primitives in order to replicate similar area and energy advantages of biological nervous systems. Discovery of ferroelectricity in doped Hafnia has thrust Ferroelectronics, specifically Ferroelectric Field-effect transistors (FeFETs), at the forefront of realizing such device platforms for future data-centric applications. Despite the utility afforded by its intrinsic properties, e.g. CMOS-compatibility and scalability, harnessing their full potential requires a cross-layer design approach combining devices, circuits, and algorithms. In this paper, we review the recent developments looking at FeFETs and their application to enable low-power on-chip learning. We outline the unique opportunities emerging from device characterization and modelling results, that ultimately translate in novel algorithms and system-level benefits.
AB - Hardware paradigms for neuromorphic computing mimic the functionalities of brain primitives in order to replicate similar area and energy advantages of biological nervous systems. Discovery of ferroelectricity in doped Hafnia has thrust Ferroelectronics, specifically Ferroelectric Field-effect transistors (FeFETs), at the forefront of realizing such device platforms for future data-centric applications. Despite the utility afforded by its intrinsic properties, e.g. CMOS-compatibility and scalability, harnessing their full potential requires a cross-layer design approach combining devices, circuits, and algorithms. In this paper, we review the recent developments looking at FeFETs and their application to enable low-power on-chip learning. We outline the unique opportunities emerging from device characterization and modelling results, that ultimately translate in novel algorithms and system-level benefits.
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U2 - 10.1109/MWSCAS57524.2023.10406022
DO - 10.1109/MWSCAS57524.2023.10406022
M3 - Conference contribution
AN - SCOPUS:85185385252
T3 - Midwest Symposium on Circuits and Systems
SP - 108
EP - 112
BT - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Y2 - 6 August 2023 through 9 August 2023
ER -