Damping Factor Based PCB Parasitic Inductance Value Optimization to Minimize Voltage Overshoot and Settling Time of Semiconductors

It is widely recognized that the parasitics of Printed Circuit Board (PCB) will influence the switching transients such as Drain-Source voltage V_DS/Collector-Emitter voltage V_CE, Gate-Source voltage V_GS/Gate-Emitter voltage V_GE, and Drain current I_D/Collector current I_C of MOSFETs/IGBTs. However, due to the packaging, the footprint of semiconductor modules, and PCB tracks, some stray inductance is unavoidable. Although designers' goal is to design a PCB with the minimized possible parasitics, an over-reduced parasitic inductance will lead to a longer settling time for switching transient and subsequently, the switching power loss will be increased. To avoid the potential suboptimized performance caused by a too small parasitic inductance, this paper proposes a method based on the power loop damping factor to find the optimal value for PCB parasitic inductance that improves switching transients such as minimizing turn-off voltage overshoot and settling time. Following the theory, the simulation and experimental results for multiple PCB designs for a SiC MOSFET switch and an IGBT module are presented. Overshoots of 7% and 6.5%, and settling times of 0.11 μs and 0.12 μs are achieved with the critically damped layout design compared to an overshoot of 29% and 22.5%, settling times of 0.78 μs and 0.47 μs using an underdamped PCB layout design for the SiC MOSFET switch and IGBT module, respectively.