Data Persistence

Vaibhav Gogte, Aasheesh Kolli, Thomas F. Wenisch

Research output: Chapter in Book/Report/Conference proceedingChapter


In a system with volatile hardware components (like CPU registers, processor caches, etc.), simply issuing a store operation does not guarantee that the update is durably written to PM. For instance, when a store operation is issued by the CPU, modern processors perform the update to a write-back cache. The write-back cache then lazily drains the update to PM, for example, when a cache line conflict occurs. Any subsequent failure erases the volatile write-back cache (or generally, any volatile component) and the update is lost. To prevent data loss on failure, hardware systems must guarantee that the updates reach PM.

Original languageEnglish (US)
Title of host publicationSynthesis Lectures on Computer Architecture
PublisherSpringer Nature
Number of pages8
StatePublished - 2022

Publication series

NameSynthesis Lectures on Computer Architecture
ISSN (Print)1935-3235
ISSN (Electronic)1935-3243

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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