@inbook{c83e9a9247a64aa2a515e9386f3c3b4c,
title = "Data Persistence",
abstract = "In a system with volatile hardware components (like CPU registers, processor caches, etc.), simply issuing a store operation does not guarantee that the update is durably written to PM. For instance, when a store operation is issued by the CPU, modern processors perform the update to a write-back cache. The write-back cache then lazily drains the update to PM, for example, when a cache line conflict occurs. Any subsequent failure erases the volatile write-back cache (or generally, any volatile component) and the update is lost. To prevent data loss on failure, hardware systems must guarantee that the updates reach PM.",
author = "Vaibhav Gogte and Aasheesh Kolli and Wenisch, {Thomas F.}",
note = "Publisher Copyright: {\textcopyright} 2022, Springer Nature Switzerland AG.",
year = "2022",
doi = "10.1007/978-3-031-79205-2_2",
language = "English (US)",
series = "Synthesis Lectures on Computer Architecture",
publisher = "Springer Nature",
pages = "13--20",
booktitle = "Synthesis Lectures on Computer Architecture",
address = "United States",
}