A tool for synthesizing systolic systems is introduced. Given a hierarchical specification of the computations to be performed and hints as to how, this tool generates an analysis of the hardware required to do the computations. The computations are specified as directed acyclic graphs, and the hints provide the temporal and topological relationships of each computation. The systolic system is synthesized by traversing the graph and marking each computation with a processor name and a time stamp. Its output can subsequently be fed to the remaining tools in the tool set to generate a VLSI fabrication description of the systolic system.