Delay and energy efficient data transmission for on-chip buses

Madhu Mutyam; Melvin Eze; Vijaykrishnan Narayanan; Yuan Xie

doi:10.1109/ISVLSI.2006.33

Delay and energy efficient data transmission for on-chip buses

Madhu Mutyam, Melvin Eze, Vijaykrishnan Narayanan, Yuan Xie

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Scopus citations

Abstract

On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the Ll cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages	355-360
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2006.33
State	Published - Oct 9 2006
Event	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany Duration: Mar 2 2006 → Mar 3 2006

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume	2006

Other

Other	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Country/Territory	Germany
City	Klarlsruhe
Period	3/2/06 → 3/3/06

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1109/ISVLSI.2006.33

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Mutyam, M., Eze, M., Narayanan, V., & Xie, Y. (2006). Delay and energy efficient data transmission for on-chip buses. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (pp. 355-360). Article 1602464 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006). https://doi.org/10.1109/ISVLSI.2006.33

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title = "Delay and energy efficient data transmission for on-chip buses",

abstract = "On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the Ll cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus.",

author = "Madhu Mutyam and Melvin Eze and Vijaykrishnan Narayanan and Yuan Xie",

year = "2006",

month = oct,

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doi = "10.1109/ISVLSI.2006.33",

language = "English (US)",

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series = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

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booktitle = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

note = "IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 ; Conference date: 02-03-2006 Through 03-03-2006",

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Mutyam, M, Eze, M, Narayanan, V & Xie, Y 2006, Delay and energy efficient data transmission for on-chip buses. in Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006., 1602464, Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, vol. 2006, pp. 355-360, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, Klarlsruhe, Germany, 3/2/06. https://doi.org/10.1109/ISVLSI.2006.33

Delay and energy efficient data transmission for on-chip buses. / Mutyam, Madhu; Eze, Melvin; Narayanan, Vijaykrishnan et al.
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 355-360 1602464 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Eze, Melvin

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N2 - On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the Ll cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus.

AB - On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the Ll cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus.

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T3 - Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

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BT - Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

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Mutyam M, Eze M, Narayanan V, Xie Y. Delay and energy efficient data transmission for on-chip buses. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 355-360. 1602464. (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006). doi: 10.1109/ISVLSI.2006.33

Delay and energy efficient data transmission for on-chip buses

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