Demonstration of Eight Metal Layer Redistribution on Glass Substrate with Fine Features and Microvia

Christopher Blancher, Mohanalingam Kathaperumal, Fuhan Liu, Madhavan Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


With increasing need for computing power, there is a demand for higher performance packaging that can enable faster communications. A promising candidate for many high-performance packaging applications is glass substrates with fine-feature (= 2µm lines and spaces) redistribution layers. Georgia Tech's Packaging Research Center has done extensive work on glass substrate packaging, and in this paper, we have developed a baseline process with optimized processing conditions to increase the number of metal layers fabricated on glass cores (substrates), and in this way increase the I/O density and performance. Double-side processing means performing processing steps on both sides of the substrate at once, rather than completing one full layer on top and then starting the bottom layer. This way of processing can eliminate the need for a carrier wafer and hence reduces the number of steps as well as complexity of processing. Fabricating high-density wiring on both sides of the substrate is beneficial in that it can reduce total layer count and create a more symmetric package which will reduce substrate warpage, and when combined with through glass via (TGV) substrates can significantly reduce the interconnection length. Furthermore, by balancing the amount of metal and polymer on either side of the substrate, total stress can be minimized. Glass is chosen as a substrate for the work presented in this paper owing to its compatibility with double-side processing and its availability at various panel sizes with and without TGVs. The dimensional stability, high planarity, and relatively low cost of glass makes it an attractive material for this application. In this paper, fabrication of an eight metal layers (8MLs) test vehicle on glass core is demonstrated by performing a thorough optimization of processing steps described in the process flow. Fabrication is performed on 300µm thick 6''× 6'' 'glass panels with < 20µm diameter microvias, 15µm line (L) and 15µm space (S) features on the inner metal layers, and 2µm L/S on the outer-most metal layers on the top and bottom. The optimized fabrication method involves a standard semi-additive process (SAP) for the inner metal layers, and an advanced semi-additive process (aSAP) using sputtered seed layer for the outer metal layers. Femtosecond laser based microvia fabrication will be presented where the fabricated via diameters are limited only by the laser spot size, and the heat affected zone (HAZ) will be minimized. Optical images measured using a 3D step profiler of samples at multiple stages of fabrication will be presented, along with the SEM images of the completed fine features on the outer-most layers.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 73rd Electronic Components and Technology Conference, ECTC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages5
ISBN (Electronic)9798350334982
StatePublished - 2023
Event73rd IEEE Electronic Components and Technology Conference, ECTC 2023 - Orlando, United States
Duration: May 30 2023Jun 2 2023

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503


Conference73rd IEEE Electronic Components and Technology Conference, ECTC 2023
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this