Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing

Siddharth Ravichandran, Vanessa Smet, Madhavan Swaminathan, Rao Tummala

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1114-1120
Number of pages7
ISBN (Electronic)9781665479431
DOIs
StatePublished - 2022
Event72nd IEEE Electronic Components and Technology Conference, ECTC 2022 - San Diego, United States
Duration: May 31 2022Jun 3 2022

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2022-May
ISSN (Print)0569-5503

Conference

Conference72nd IEEE Electronic Components and Technology Conference, ECTC 2022
Country/TerritoryUnited States
CitySan Diego
Period5/31/226/3/22

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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