Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing

Siddharth Ravichandran; Vanessa Smet; Madhavan Swaminathan; Rao Tummala

doi:10.1109/ECTC51906.2022.00180

Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing

Siddharth Ravichandran, Vanessa Smet, Madhavan Swaminathan, Rao Tummala

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.

Original language	English (US)
Title of host publication	Proceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1114-1120
Number of pages	7
ISBN (Electronic)	9781665479431
DOIs	https://doi.org/10.1109/ECTC51906.2022.00180
State	Published - 2022
Event	72nd IEEE Electronic Components and Technology Conference, ECTC 2022 - San Diego, United States Duration: May 31 2022 → Jun 3 2022

Publication series

Name	Proceedings - Electronic Components and Technology Conference
Volume	2022-May
ISSN (Print)	0569-5503

Conference

Conference	72nd IEEE Electronic Components and Technology Conference, ECTC 2022
Country/Territory	United States
City	San Diego
Period	5/31/22 → 6/3/22

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ECTC51906.2022.00180

Cite this

Ravichandran, S., Smet, V., Swaminathan, M., & Tummala, R. (2022). Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing. In Proceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022 (pp. 1114-1120). (Proceedings - Electronic Components and Technology Conference; Vol. 2022-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC51906.2022.00180

Ravichandran, Siddharth ; Smet, Vanessa ; Swaminathan, Madhavan et al. / Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing. Proceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 1114-1120 (Proceedings - Electronic Components and Technology Conference).

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title = "Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing",

abstract = "This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.",

author = "Siddharth Ravichandran and Vanessa Smet and Madhavan Swaminathan and Rao Tummala",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 72nd IEEE Electronic Components and Technology Conference, ECTC 2022 ; Conference date: 31-05-2022 Through 03-06-2022",

year = "2022",

doi = "10.1109/ECTC51906.2022.00180",

language = "English (US)",

series = "Proceedings - Electronic Components and Technology Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Ravichandran, S, Smet, V, Swaminathan, M & Tummala, R 2022, Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing. in Proceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022. Proceedings - Electronic Components and Technology Conference, vol. 2022-May, Institute of Electrical and Electronics Engineers Inc., pp. 1114-1120, 72nd IEEE Electronic Components and Technology Conference, ECTC 2022, San Diego, United States, 5/31/22. https://doi.org/10.1109/ECTC51906.2022.00180

Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing. / Ravichandran, Siddharth; Smet, Vanessa; Swaminathan, Madhavan et al.
Proceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 1114-1120 (Proceedings - Electronic Components and Technology Conference; Vol. 2022-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Ravichandran, Siddharth

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AU - Swaminathan, Madhavan

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AB - This paper presents a technology demonstration of two novel 3D glass-based architectures for high performance computing applications. Current 3D technologies are limited by Through Silicon Vias (TSVs), and the proposed approached based on Glass Panel Embedding (GPE) eliminates TSVs resulting in a more robust 3D packaging platform that supports a variety of architectures. Two such architectures are designed and demonstrated in this paper. The first test vehicle shows multiple dies embedded and interconnected in a glass cavity, along with dies assembled on top using a microbump interface. The second test vehicle shows a 50x50 mm glass interposer package with 4 dies embedded in the core, 8 HBM emulators & 2 large SoCs assembled on top at 35 micron-bump pitch.

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Ravichandran S, Smet V, Swaminathan M, Tummala R. Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing. In Proceedings - IEEE 72nd Electronic Components and Technology Conference, ECTC 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 1114-1120. (Proceedings - Electronic Components and Technology Conference). doi: 10.1109/ECTC51906.2022.00180

Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing

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