Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

D. K. Mohata; R. Bijesh; Y. Zhu; M. K. Hudait; R. Southwick; Z. Chbili; D. Gundlach; J. Suehle; J. M. Fastenau; D. Loubychev; A. K. Liu; T. S. Mayer; V. Narayanan; S. Datta

doi:10.1109/VLSIT.2012.6242457

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

D. K. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A. K. Liu, T. S. Mayer, V. Narayanan, S. Datta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

67 Scopus citations

Abstract

Staggered tunnel junction (GaAs _0.35Sb _0.65/In _0.7Ga _0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I _on, of 135μA/μm and highest I _on/I _off ratio of 2.7×10 ⁴ (V _ds=0.5V, V _on=V _off=1.5V). Effective oxide thickness (EOT) scaling (using Al ₂O ₃/HfO ₂ bilayer gate stack) coupled with pulsed I-V measurements (suppressing D _it response) enable demonstration of steeper switching TFET.

Original language	English (US)
Title of host publication	2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages	53-54
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2012.6242457
State	Published - 2012
Event	2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States Duration: Jun 12 2012 → Jun 14 2012

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2012 Symposium on VLSI Technology, VLSIT 2012
Country/Territory	United States
City	Honolulu, HI
Period	6/12/12 → 6/14/12

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2012.6242457

Cite this

Mohata, D. K., Bijesh, R., Zhu, Y., Hudait, M. K., Southwick, R., Chbili, Z., Gundlach, D., Suehle, J., Fastenau, J. M., Loubychev, D., Liu, A. K., Mayer, T. S., Narayanan, V., & Datta, S. (2012). Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio. In 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers (pp. 53-54). Article 6242457 (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2012.6242457

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title = "Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio",

abstract = "Staggered tunnel junction (GaAs 0.35Sb 0.65/In 0.7Ga 0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I on, of 135μA/μm and highest I on/I off ratio of 2.7×10 4 (V ds=0.5V, V on=V off=1.5V). Effective oxide thickness (EOT) scaling (using Al 2O 3/HfO 2 bilayer gate stack) coupled with pulsed I-V measurements (suppressing D it response) enable demonstration of steeper switching TFET.",

author = "Mohata, {D. K.} and R. Bijesh and Y. Zhu and Hudait, {M. K.} and R. Southwick and Z. Chbili and D. Gundlach and J. Suehle and Fastenau, {J. M.} and D. Loubychev and Liu, {A. K.} and Mayer, {T. S.} and V. Narayanan and S. Datta",

year = "2012",

doi = "10.1109/VLSIT.2012.6242457",

language = "English (US)",

isbn = "9781467308458",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "53--54",

booktitle = "2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers",

}

Mohata, DK, Bijesh, R, Zhu, Y, Hudait, MK, Southwick, R, Chbili, Z, Gundlach, D, Suehle, J, Fastenau, JM, Loubychev, D, Liu, AK, Mayer, TS, Narayanan, V & Datta, S 2012, Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio. in 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers., 6242457, Digest of Technical Papers - Symposium on VLSI Technology, pp. 53-54, 2012 Symposium on VLSI Technology, VLSIT 2012, Honolulu, HI, United States, 6/12/12. https://doi.org/10.1109/VLSIT.2012.6242457

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio. / Mohata, D. K.; Bijesh, R.; Zhu, Y. et al.
2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. 2012. p. 53-54 6242457 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Hudait, M. K.

AU - Southwick, R.

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AU - Gundlach, D.

AU - Suehle, J.

AU - Fastenau, J. M.

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AU - Narayanan, V.

AU - Datta, S.

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AB - Staggered tunnel junction (GaAs 0.35Sb 0.65/In 0.7Ga 0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I on, of 135μA/μm and highest I on/I off ratio of 2.7×10 4 (V ds=0.5V, V on=V off=1.5V). Effective oxide thickness (EOT) scaling (using Al 2O 3/HfO 2 bilayer gate stack) coupled with pulsed I-V measurements (suppressing D it response) enable demonstration of steeper switching TFET.

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Mohata DK, Bijesh R, Zhu Y, Hudait MK, Southwick R, Chbili Z et al. Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio. In 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. 2012. p. 53-54. 6242457. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2012.6242457

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

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