@inproceedings{954d50b8b2a34d658d551a520a072fec,
title = "Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic",
abstract = "Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at -VDS=0.5V. The p-type TFET (PTFET) has ION =30μA/μm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275μA/μm and ION/IOFF=3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low VDD logic applications.",
author = "R. Pandey and H. Madan and H. Liu and V. Chobpattana and M. Barth and B. Rajamohanan and Hollander, {M. J.} and T. Clark and K. Wang and Kim, {J. H.} and D. Gundlach and Cheung, {K. P.} and J. Suehle and R. Engel-Herbert and S. Stemmer and S. Datta",
note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; Symposium on VLSI Technology, VLSI Technology 2015 ; Conference date: 16-06-2015 Through 18-06-2015",
year = "2015",
month = aug,
day = "25",
doi = "10.1109/VLSIT.2015.7223676",
language = "English (US)",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T206--T207",
booktitle = "2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers",
address = "United States",
}