Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic

R. Pandey; H. Madan; H. Liu; V. Chobpattana; M. Barth; B. Rajamohanan; M. J. Hollander; T. Clark; K. Wang; J. H. Kim; D. Gundlach; K. P. Cheung; J. Suehle; R. Engel-Herbert; S. Stemmer; S. Datta

doi:10.1109/VLSIT.2015.7223676

Demonstration of p-type In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 and n-type GaAs_0.4Sb_0.6/In_0.65Ga_0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic

R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. J. Hollander, T. Clark, K. Wang, J. H. Kim, D. Gundlach, K. P. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, S. Datta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

54 Scopus citations

Abstract

Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at -V_DS=0.5V. The p-type TFET (PTFET) has I_ON =30μA/μm and I_ON/I_OFF =10⁵, whereas the n-type TFET (NTFET) has I_ON =275μA/μm and I_ON/I_OFF=3×10⁵, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V_DD logic applications.

Original language	English (US)
Title of host publication	2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T206-T207
ISBN (Electronic)	9784863485013
DOIs	https://doi.org/10.1109/VLSIT.2015.7223676
State	Published - Aug 25 2015
Event	Symposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan Duration: Jun 16 2015 → Jun 18 2015

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2015-August
ISSN (Print)	0743-1562

Other

Other	Symposium on VLSI Technology, VLSI Technology 2015
Country/Territory	Japan
City	Kyoto
Period	6/16/15 → 6/18/15

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2015.7223676

Cite this

Pandey, R., Madan, H., Liu, H., Chobpattana, V., Barth, M., Rajamohanan, B., Hollander, M. J., Clark, T., Wang, K., Kim, J. H., Gundlach, D., Cheung, K. P., Suehle, J., Engel-Herbert, R., Stemmer, S., & Datta, S. (2015). Demonstration of p-type In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 and n-type GaAs_0.4Sb_0.6/In_0.65Ga_0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (pp. T206-T207). Article 7223676 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223676

Pandey, R. ; Madan, H. ; Liu, H. et al. / Demonstration of p-type In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 and n-type GaAs_0.4Sb_0.6/In_0.65Ga_0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic. 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. T206-T207 (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic",

abstract = "Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at -VDS=0.5V. The p-type TFET (PTFET) has ION =30μA/μm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275μA/μm and ION/IOFF=3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low VDD logic applications.",

author = "R. Pandey and H. Madan and H. Liu and V. Chobpattana and M. Barth and B. Rajamohanan and Hollander, {M. J.} and T. Clark and K. Wang and Kim, {J. H.} and D. Gundlach and Cheung, {K. P.} and J. Suehle and R. Engel-Herbert and S. Stemmer and S. Datta",

note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; Symposium on VLSI Technology, VLSI Technology 2015 ; Conference date: 16-06-2015 Through 18-06-2015",

year = "2015",

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doi = "10.1109/VLSIT.2015.7223676",

language = "English (US)",

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Pandey, R, Madan, H, Liu, H, Chobpattana, V, Barth, M, Rajamohanan, B, Hollander, MJ, Clark, T, Wang, K, Kim, JH, Gundlach, D, Cheung, KP, Suehle, J, Engel-Herbert, R, Stemmer, S & Datta, S 2015, Demonstration of p-type In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 and n-type GaAs_0.4Sb_0.6/In_0.65Ga_0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic. in 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers., 7223676, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. T206-T207, Symposium on VLSI Technology, VLSI Technology 2015, Kyoto, Japan, 6/16/15. https://doi.org/10.1109/VLSIT.2015.7223676

Demonstration of p-type In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 and n-type GaAs_0.4Sb_0.6/In_0.65Ga_0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic. / Pandey, R.; Madan, H.; Liu, H. et al.
2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. T206-T207 7223676 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Pandey, R.

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AU - Wang, K.

AU - Kim, J. H.

AU - Gundlach, D.

AU - Cheung, K. P.

AU - Suehle, J.

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AU - Datta, S.

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N2 - Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at -VDS=0.5V. The p-type TFET (PTFET) has ION =30μA/μm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275μA/μm and ION/IOFF=3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low VDD logic applications.

AB - Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at -VDS=0.5V. The p-type TFET (PTFET) has ION =30μA/μm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275μA/μm and ION/IOFF=3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low VDD logic applications.

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M3 - Conference contribution

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Pandey R, Madan H, Liu H, Chobpattana V, Barth M, Rajamohanan B et al. Demonstration of p-type In_0.7Ga_0.3As/GaAs_0.35Sb_0.65 and n-type GaAs_0.4Sb_0.6/In_0.65Ga_0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. T206-T207. 7223676. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2015.7223676