TY - JOUR
T1 - Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory
AU - Xiao, Yi
AU - Deng, Shan
AU - Jiang, Zhouhang
AU - Qin, Yixin
AU - Zhao, Zijian
AU - Zhang, Renzheng
AU - Howe, John
AU - Lee, Yushan
AU - Duan, Jiahui
AU - Joshi, Rajiv
AU - Kampfe, Thomas
AU - Luo, Tengfei
AU - Hou, Tuo Hung
AU - Gong, Xiao
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal–ferroelectric–metal (MFM)capacitors, to demonstrate a high-performance and highdensity 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance (CFE) enables self-boosted inhibition under the V W/2 scheme, but renders the V W/3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs (CZ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.
AB - In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal–ferroelectric–metal (MFM)capacitors, to demonstrate a high-performance and highdensity 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance (CFE) enables self-boosted inhibition under the V W/2 scheme, but renders the V W/3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs (CZ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.
UR - https://www.scopus.com/pages/publications/105004644194
UR - https://www.scopus.com/inward/citedby.url?scp=105004644194&partnerID=8YFLogxK
U2 - 10.1109/TED.2025.3564273
DO - 10.1109/TED.2025.3564273
M3 - Article
AN - SCOPUS:105004644194
SN - 0018-9383
VL - 72
SP - 3327
EP - 3334
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 6
ER -