TY - GEN
T1 - Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs
AU - Anwar, Mohd
AU - Azeemuddin, Syed
AU - Khan, Mohammed Zafar Ali
PY - 2013
Y1 - 2013
N2 - In this paper, we present a noise cancellation technique for common gate ultra wide band (UWB) low noise amplifiers (LNAs) which not only reduces the noise but also increases the gain. On implementing this technique in one of the existing UWB LNAs significant reduction of noise figure (NF) compared to same LNA without noise cancellation technique was observed. Noise cancellation of the most dominating thermal noise source viz. the input matching device with theoretical analysis is presented in this paper. Simulation results with TSMC 0.18 (m CMOSRF technology shows a peak gain of 28 dB and base NF of 3.16 dB for a 6.6 GHz (2.4-9 GHz) band LNA with noise cancellation when compared to peak gain of 21 dB and base NF of 4.09 dB without noise cancellation. Both theoretical analysis and simulation results are in good agreement.
AB - In this paper, we present a noise cancellation technique for common gate ultra wide band (UWB) low noise amplifiers (LNAs) which not only reduces the noise but also increases the gain. On implementing this technique in one of the existing UWB LNAs significant reduction of noise figure (NF) compared to same LNA without noise cancellation technique was observed. Noise cancellation of the most dominating thermal noise source viz. the input matching device with theoretical analysis is presented in this paper. Simulation results with TSMC 0.18 (m CMOSRF technology shows a peak gain of 28 dB and base NF of 3.16 dB for a 6.6 GHz (2.4-9 GHz) band LNA with noise cancellation when compared to peak gain of 21 dB and base NF of 4.09 dB without noise cancellation. Both theoretical analysis and simulation results are in good agreement.
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U2 - 10.1007/978-3-642-42024-5_21
DO - 10.1007/978-3-642-42024-5_21
M3 - Conference contribution
AN - SCOPUS:84904633261
SN - 9783642420238
T3 - Communications in Computer and Information Science
SP - 169
EP - 176
BT - VLSI Design and Test - 17th International Symposium, VDAT 2013, Revised Selected Papers
PB - Springer Verlag
T2 - 17th International Symposium on VLSI Design and Test Symposium, VDAT 2013
Y2 - 27 July 2013 through 30 July 2013
ER -