Design and analysis of an NoC architecture from performance, reliability and energy perspective

Keyphrases

• Performance Reliability 100%
• Router 100%
• Network on chip 100%
• Performance Aspects 100%
• Energy Perspective 100%
• Network-on-chip Architectures 100%
• Evaluating Performance 66%
• High Performance 33%
• Area Overhead 33%
• Analytical Model 33%
• Fault Tolerance 33%
• Energy Consumption 33%
• Energy Efficiency 33%
• Reliability Issues 33%
• Average Energy 33%
• Performance Tradeoff 33%
• Upsetting 33%
• Transient Fault 33%
• Queuing Theory 33%
• Performance Efficiency 33%
• Theory Model 33%
• Energy Behaviour 33%
• Performance Behavior 33%
• Hardware Components 33%
• Average Latency 33%
• Error Protection 33%
• Energy Reliability 33%
• Protection Scheme 33%
• Fast Method 33%
• Latency-sensitive Applications 33%
• Reliability Performance 33%
• Energy Overhead 33%
• System-on-chip Design 33%
• Complete Solution 33%
• Protection Method 33%
• Error Correction Mechanism 33%
• Cycle-accurate Simulator 33%
• Deep Submicron Technology 33%
• Router Architecture 33%

Computer Science

• Networks on Chips 100%
• Chip Architecture 100%
• fault-tolerance 20%
• Analytical Model 20%
• Energy Consumption 20%
• Energy Efficiency 20%
• Error Correction 20%
• Transient Fault 20%
• Error Detection 20%
• Average Latency 20%
• Protection Scheme 20%
• Hardware Component 20%
• Router Architecture 20%
• Cycle-Accurate Simulator 20%
• Protection Technique 20%
• Queuing Theory 20%
• System-on-Chip 20%

Engineering

• Network-on-Chip 100%
• Chip Architecture 100%
• Transients 20%
• Energy Conservation 20%
• Analytical Model 20%
• Fits and Tolerances 20%
• Energy Efficiency 20%
• Hardware Component 20%
• Error Detection 20%
• Protection Scheme 20%
• Error Correction 20%
• System-on-Chip 20%
• Reliability Issue 20%
• Complete Solution 20%
• Energy Behavior 20%