Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs)

This paper for the first time proposes and demonstrates the use of panel-based polycrystalline silicon interposers for highest I/Os at lowest cost. Such an interposer is targeted at roughly a 10 lower cost compared to wafer based silicon interposers with through silicon vias (TSVs) and back end of line (BEOL) re-distribution layers (RDL). Laser via ablation was used to demonstrate through package vias (TPVs) as small as 10m diameter in 220m thin polycrystalline silicon panels made without any chemical-mechanical polishing (CMP). A thick polymer via liner and stress buffer layer was formed in the silicon TPVs to replace oxide liners and diffusion barriers used in TSVs. A panel silicon interposer test vehicle process demonstrator was fabricated and initial electrical measurements indicate much lower loss compared to CMOS silicon interposer with thin oxide liners. Electrical and mechanical design and modeling was also carried out to provide design guidelines for TPV formation.