Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs

Sung Joo Park; Madhavan Swaminathan; Nitish Natu; Byunghyun Lee; Sang Min Lee; Woong Hwan Ryu; Kee Sup Kim

doi:10.1109/EPEPS.2014.7103613

Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs

Sung Joo Park, Madhavan Swaminathan, Nitish Natu, Byunghyun Lee, Sang Min Lee, Woong Hwan Ryu, Kee Sup Kim

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Clock Distribution Networks (CDN) in three dimensional ICs face problems due to temperature and gradients observed across the die. The propagation delay of paths in the CDN varies and leads to mismatch in skew at the distribution points. This could potentially harm the system by violating setup and hold timing constraints. Compensation techniques can however be integrated with the CDN to compensate for the effects due to thermal gradients. Two such techniques called adaptive supply voltage and controllable path delay were implemented and are presented in this paper. An FPGA-based test vehicle was used to validate these techniques. Finally the overhead of area and power is analyzed and the performance improvement is observed.

Original language	English (US)
Title of host publication	2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	127-130
Number of pages	4
ISBN (Electronic)	9781479936410
DOIs	https://doi.org/10.1109/EPEPS.2014.7103613
State	Published - 2014
Event	23rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014 - Portland, United States Duration: Oct 26 2014 → Oct 29 2014

Publication series

Name	2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014

Conference

Conference	23rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014
Country/Territory	United States
City	Portland
Period	10/26/14 → 10/29/14

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EPEPS.2014.7103613

Cite this

Park, S. J., Swaminathan, M., Natu, N., Lee, B., Lee, S. M., Ryu, W. H., & Kim, K. S. (2014). Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs. In 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014 (pp. 127-130). Article 7103613 (2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEPS.2014.7103613

Park, Sung Joo ; Swaminathan, Madhavan ; Natu, Nitish et al. / Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs. 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 127-130 (2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014).

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title = "Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs",

abstract = "Clock Distribution Networks (CDN) in three dimensional ICs face problems due to temperature and gradients observed across the die. The propagation delay of paths in the CDN varies and leads to mismatch in skew at the distribution points. This could potentially harm the system by violating setup and hold timing constraints. Compensation techniques can however be integrated with the CDN to compensate for the effects due to thermal gradients. Two such techniques called adaptive supply voltage and controllable path delay were implemented and are presented in this paper. An FPGA-based test vehicle was used to validate these techniques. Finally the overhead of area and power is analyzed and the performance improvement is observed.",

author = "Park, {Sung Joo} and Madhavan Swaminathan and Nitish Natu and Byunghyun Lee and Lee, {Sang Min} and Ryu, {Woong Hwan} and Kim, {Kee Sup}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 23rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014 ; Conference date: 26-10-2014 Through 29-10-2014",

year = "2014",

doi = "10.1109/EPEPS.2014.7103613",

language = "English (US)",

series = "2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Park, SJ, Swaminathan, M, Natu, N, Lee, B, Lee, SM, Ryu, WH & Kim, KS 2014, Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs. in 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014., 7103613, 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014, Institute of Electrical and Electronics Engineers Inc., pp. 127-130, 23rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014, Portland, United States, 10/26/14. https://doi.org/10.1109/EPEPS.2014.7103613

Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs. / Park, Sung Joo; Swaminathan, Madhavan; Natu, Nitish et al.
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 127-130 7103613 (2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Park, Sung Joo

AU - Swaminathan, Madhavan

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AB - Clock Distribution Networks (CDN) in three dimensional ICs face problems due to temperature and gradients observed across the die. The propagation delay of paths in the CDN varies and leads to mismatch in skew at the distribution points. This could potentially harm the system by violating setup and hold timing constraints. Compensation techniques can however be integrated with the CDN to compensate for the effects due to thermal gradients. Two such techniques called adaptive supply voltage and controllable path delay were implemented and are presented in this paper. An FPGA-based test vehicle was used to validate these techniques. Finally the overhead of area and power is analyzed and the performance improvement is observed.

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Park SJ, Swaminathan M, Natu N, Lee B, Lee SM, Ryu WH et al. Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs. In 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 127-130. 7103613. (2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014). doi: 10.1109/EPEPS.2014.7103613

Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs

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