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Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs
Sung Joo Park, Madhavan Swaminathan, Nitish Natu, Byunghyun Lee, Sang Min Lee, Woong Hwan Ryu, Kee Sup Kim
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Scopus
citations