TY - GEN
T1 - Design and Implementation of a Real-time Parallel FFT for a Direction-Finding System on an FPGA
AU - Pradeep, Bheema Lakshmi
AU - Anand, Rishu
AU - Vadakattu, Pavan
AU - Azemuddin, Syed
AU - Ahmed, Aquibuddin
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - An FFT is an essential algorithm for radar signal processing in a radar system. Due to increase in computational power of FPGAs, it is possible to perform FFT operation onboard in an airborne vehicle. However, the FPGA resources have become a limitation for processing real-time signals using conventional methods. To address this issue, we have proposed a parallel pipelined FFT architecture that can achieve very high throughput with very low latency, making it capable of processing real-time continuous data. This architecture is implemented in a radar system, which works from L band to Ku band. In this radar system, the received RF signal is downconverted into an IF signal of 1 GHz frequency with a 500 MHz bandwidth and converted to digital data using a 10-bit ADC. On the converted digital data, a 512-point FFT is implemented on a Xilinx Virtex-7 XC7VX485T FPGA using 8 parallel channels with 64 data frames and is compared with the conventional IP core-based architecture. The proposed architecture takes 1.307μs to implement FFT, which is 5.15 times faster than the IP core-based architecture and requires fewer arithmetic computations. The overall total number of complex multiplications, complex additions, multipliers & adders were reduced by 10.42%, 30.64%, 10.42% & 23.90% respectively. Apart from very low latency and fewer arithmetic operations, the proposed parallel FFT architecture achieved a throughput of 1.350 Giga Samples per second (Gsps).
AB - An FFT is an essential algorithm for radar signal processing in a radar system. Due to increase in computational power of FPGAs, it is possible to perform FFT operation onboard in an airborne vehicle. However, the FPGA resources have become a limitation for processing real-time signals using conventional methods. To address this issue, we have proposed a parallel pipelined FFT architecture that can achieve very high throughput with very low latency, making it capable of processing real-time continuous data. This architecture is implemented in a radar system, which works from L band to Ku band. In this radar system, the received RF signal is downconverted into an IF signal of 1 GHz frequency with a 500 MHz bandwidth and converted to digital data using a 10-bit ADC. On the converted digital data, a 512-point FFT is implemented on a Xilinx Virtex-7 XC7VX485T FPGA using 8 parallel channels with 64 data frames and is compared with the conventional IP core-based architecture. The proposed architecture takes 1.307μs to implement FFT, which is 5.15 times faster than the IP core-based architecture and requires fewer arithmetic computations. The overall total number of complex multiplications, complex additions, multipliers & adders were reduced by 10.42%, 30.64%, 10.42% & 23.90% respectively. Apart from very low latency and fewer arithmetic operations, the proposed parallel FFT architecture achieved a throughput of 1.350 Giga Samples per second (Gsps).
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U2 - 10.1109/HPEC55821.2022.9926310
DO - 10.1109/HPEC55821.2022.9926310
M3 - Conference contribution
AN - SCOPUS:85142270902
T3 - 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022
BT - 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE High Performance Extreme Computing Conference, HPEC 2022
Y2 - 19 September 2022 through 23 September 2022
ER -