Design and management of 3D chip multiprocessors using network-in-memory

Feihui Li, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie, Vijaykrishnan Narayanan, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

305 Citations (SciVal)


Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the current trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this paper is to study the challenges for L2 design and management in 3D chip multiprocessors. Our first contribution is to propose a router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory. Our second contribution is to demonstrate, through extensive experiments, that a 3D L2 memory architecture generates much better results than the conventional two-dimensional (2D) designs under different number of layers and vertical (inter-wafer) connections. In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration. This also helps reduce power consumption in L2 due to a reduced number of data movements.

Original languageEnglish (US)
Title of host publicationProceedings - 33rd International Symposium on Computer Architecture,ISCA 2006
Number of pages12
StatePublished - 2006
Event33rd International Symposium on Computer Architecture, ISCA 2006 - Boston, MA, United States
Duration: Jun 17 2006Jun 21 2006

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


Other33rd International Symposium on Computer Architecture, ISCA 2006
Country/TerritoryUnited States
CityBoston, MA

All Science Journal Classification (ASJC) codes

  • General Engineering


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