Design and use of SimplePower: a cycle-accurate energy estimation tool

W. Ye, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

355 Scopus citations


In this paper, we present the design and use of a comprehensive framework, SimplePower, for evaluating the effects of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT level energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also provides the energy consumed in the memory system and on-chip buses using analytical energy models. We present the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a power-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively.

Original languageEnglish (US)
Pages (from-to)340-345
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - Jan 1 2000
EventDAC 2000: 37th Design Automation Conference - Los Angeles, CA, USA
Duration: Jun 5 2000Jun 9 2000

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering


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