Design considerations for databus charge recovery

Benjamin Bishop, Victor Lyuboslavsky, N. Vijaykrishnan, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


The charge recovery databus is a scheme which reduce energy consumption through the application of adiabatic circuit techniques. Previous work [2] gives a solid theoretical analysis of this scheme, including quantitative data assuming random bus values. We extend this earlier work by presenting a quantitative analysis of the charge recovery databus using 15 benchmarks and four high-level bus coding schemes. We show that a very simple implementation of the charge recovery databus is capable of reducing average energy consumption by 28% beyond traditional high-level bus encoding techniques. In addition, we examine delay and energy consumption in the added hardware.

Original languageEnglish (US)
Pages (from-to)104-106
Number of pages3
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
StatePublished - Feb 2001

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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