Design methodologies for high density domain wall memory

Swaroop Ghosh

doi:10.1109/NanoArch.2013.6623035

Design methodologies for high density domain wall memory

Swaroop Ghosh

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Scopus citations

Abstract

Domain wall memory (DWM) has emerged as a possible candidate for embedded cache application. The fundamental advantage of DWM is its MLC (multi-level cell) capability allowing it to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we address design challenges associated with DWM for potential use in on-chip cache.

Original language	English (US)
Title of host publication	Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013
Pages	30-31
Number of pages	2
DOIs	https://doi.org/10.1109/NanoArch.2013.6623035
State	Published - 2013
Event	2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013 - New York City, NY, United States Duration: Jul 15 2013 → Jul 17 2013

Publication series

Name	Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013

Other

Other	2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013
Country/Territory	United States
City	New York City, NY
Period	7/15/13 → 7/17/13

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/NanoArch.2013.6623035

Cite this

@inproceedings{dfa18f60cb604971b53e942154545b64,

title = "Design methodologies for high density domain wall memory",

abstract = "Domain wall memory (DWM) has emerged as a possible candidate for embedded cache application. The fundamental advantage of DWM is its MLC (multi-level cell) capability allowing it to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we address design challenges associated with DWM for potential use in on-chip cache.",

author = "Swaroop Ghosh",

year = "2013",

doi = "10.1109/NanoArch.2013.6623035",

language = "English (US)",

isbn = "9781479908738",

series = "Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013",

pages = "30--31",

booktitle = "Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013",

note = "2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013 ; Conference date: 15-07-2013 Through 17-07-2013",

}

Ghosh, S 2013, Design methodologies for high density domain wall memory. in Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013., 6623035, Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013, pp. 30-31, 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013, New York City, NY, United States, 7/15/13. https://doi.org/10.1109/NanoArch.2013.6623035

Design methodologies for high density domain wall memory. / Ghosh, Swaroop.
Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013. 2013. p. 30-31 6623035 (Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Design methodologies for high density domain wall memory

AU - Ghosh, Swaroop

PY - 2013

Y1 - 2013

N2 - Domain wall memory (DWM) has emerged as a possible candidate for embedded cache application. The fundamental advantage of DWM is its MLC (multi-level cell) capability allowing it to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we address design challenges associated with DWM for potential use in on-chip cache.

AB - Domain wall memory (DWM) has emerged as a possible candidate for embedded cache application. The fundamental advantage of DWM is its MLC (multi-level cell) capability allowing it to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we address design challenges associated with DWM for potential use in on-chip cache.

UR - http://www.scopus.com/inward/record.url?scp=84886770550&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84886770550&partnerID=8YFLogxK

U2 - 10.1109/NanoArch.2013.6623035

DO - 10.1109/NanoArch.2013.6623035

M3 - Conference contribution

AN - SCOPUS:84886770550

SN - 9781479908738

T3 - Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013

SP - 30

EP - 31

BT - Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013

T2 - 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013

Y2 - 15 July 2013 through 17 July 2013

ER -

Design methodologies for high density domain wall memory

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this