Design of a dynamic priority-based fast path architecture for on-chip interconnects

In modern multi-core System-on-Chip (SoC) architectures, the design of innovative interconnection fabrics is indispensable. The concept of the Network-on-Chip (NoC) architecture has been proposed recently to better suit this requirement. Especially, the router architecture has a significant effect on the overall performance and energy consumption of the chip. We propose a dynamic path management scheme that exploits network traffic information during switch arbitration. Consequently, flits transferred across frequently used paths are expedited by traversing a reduced router pipeline. This technique, based on pipeline bypassing, is simulated and evaluated in terms of network latency and average power consumption. Simulation results with real-world application traces show that the architecture improves the performance up to 30% while incurring only minimal area / power overhead.