@inproceedings{a5de6abc4cb341b0a100a7ec8044cb8c,
title = "Design of a nanosensor array architecture",
abstract = "This paper describes a nanowire sensor array architecture for high-speed, high-accuracy sensor systems. The chip has very simple processing elements (PEs) in a massively parallel architecture, in which each PE is directly connected to seven sensors. A sampling rate of 100 ns is enough to realized high-speed sensing feedback for electronic nose. We aim to create a very simple architecture, because a compact design is required to integrate as many PEs as possible on a single chip. A widely used, easy to implement estimator - minimum distance classifier is introduced to realize the pattern recognition. A sample design is implemented in VHDL and has been simulated and synthesized using TSMC 0.25 standard cell library and a commercial 0.16 standard cell library.",
author = "Wei Xu and N. Vijaykrishnan and Y. Xie and Irwin, {M. J.}",
year = "2004",
doi = "10.1145/988952.989024",
language = "English (US)",
isbn = "1581138539",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI",
publisher = "Association for Computing Machinery (ACM)",
pages = "298--303",
booktitle = "Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004",
address = "United States",
note = "Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era ; Conference date: 26-04-2004 Through 28-04-2004",
}