Abstract
Register renaming is often used to improve performance in many high-ILP processors. However, there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| Publisher | IEEE |
| Pages | 34-37 |
| Number of pages | 4 |
| ISBN (Print) | 0769501044 |
| State | Published - 1999 |
| Event | Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Duration: Mar 4 1999 → Mar 6 1999 |
Other
| Other | Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) |
|---|---|
| City | Ann Arbor, MI, USA |
| Period | 3/4/99 → 3/6/99 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering