DESIGN OF AN INTEGRATED RNS DIGITAL FILTER MODULE BASED ON SERIAL-BY-MODULUS ARITHMETIC.

W. K. Jenkins; S. F. Lao

DESIGN OF AN INTEGRATED RNS DIGITAL FILTER MODULE BASED ON SERIAL-BY-MODULUS ARITHMETIC.

W. K. Jenkins
, S. F. Lao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The use of residue number system (RNS) arithmetic to designing high-speed special-purpose digital hardware that is suitable for VLSI implementation is considered. A processor architecture based on serial-by-modulus (SBM) RNS arithmetic is presented. Although slower in speed, SBM-RNS architectures are conservative in terms of silicon area and provide a mechanism for realizing high-precision signal processors in VLSI circuits of relatively short wordlength.

Original language	English (US)
Title of host publication	Unknown Host Publication Title
Publisher	IEEE
Pages	634-637
Number of pages	4
ISBN (Print)	0818608021
State	Published - Dec 1 1987

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

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title = "DESIGN OF AN INTEGRATED RNS DIGITAL FILTER MODULE BASED ON SERIAL-BY-MODULUS ARITHMETIC.",

abstract = "The use of residue number system (RNS) arithmetic to designing high-speed special-purpose digital hardware that is suitable for VLSI implementation is considered. A processor architecture based on serial-by-modulus (SBM) RNS arithmetic is presented. Although slower in speed, SBM-RNS architectures are conservative in terms of silicon area and provide a mechanism for realizing high-precision signal processors in VLSI circuits of relatively short wordlength.",

author = "Jenkins, \{W. K.\} and Lao, \{S. F.\}",

year = "1987",

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publisher = "IEEE",

pages = "634--637",

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AU - Lao, S. F.

PY - 1987/12/1

Y1 - 1987/12/1

N2 - The use of residue number system (RNS) arithmetic to designing high-speed special-purpose digital hardware that is suitable for VLSI implementation is considered. A processor architecture based on serial-by-modulus (SBM) RNS arithmetic is presented. Although slower in speed, SBM-RNS architectures are conservative in terms of silicon area and provide a mechanism for realizing high-precision signal processors in VLSI circuits of relatively short wordlength.

AB - The use of residue number system (RNS) arithmetic to designing high-speed special-purpose digital hardware that is suitable for VLSI implementation is considered. A processor architecture based on serial-by-modulus (SBM) RNS arithmetic is presented. Although slower in speed, SBM-RNS architectures are conservative in terms of silicon area and provide a mechanism for realizing high-precision signal processors in VLSI circuits of relatively short wordlength.

UR - https://www.scopus.com/pages/publications/0023533412

UR - https://www.scopus.com/pages/publications/0023533412#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0023533412

SN - 0818608021

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EP - 637

BT - Unknown Host Publication Title

PB - IEEE

ER -

DESIGN OF AN INTEGRATED RNS DIGITAL FILTER MODULE BASED ON SERIAL-BY-MODULUS ARITHMETIC.

Abstract

All Science Journal Classification (ASJC) codes

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