TY - JOUR
T1 - Design of databus charge recovery mechanism
AU - Lyuboslavsky, Victor
AU - Bishop, Benjamin
AU - Narayanan, Vijaykrishnan
AU - Irwin, Mary Jane
PY - 2000
Y1 - 2000
N2 - We present a design for a charge recovery databus. Previous works have laid the groundwork for our design, presenting the theory that would make adiabatic circuit techniques useful. During a shorting period, the charge is transferred from the falling bit-lines to precharge the rising bit-lines while both the sender and the receiver are off. We simulate this 8-bit charge recovery bus with data based on realistic benchmarks. The power savings average 20% over typical on-chip and off-chip bus capacitances. The savings increase with larger bus capacitances and longer shorting times. The overhead of the control circuitry is estimated at 3.6% of the total power consumption.
AB - We present a design for a charge recovery databus. Previous works have laid the groundwork for our design, presenting the theory that would make adiabatic circuit techniques useful. During a shorting period, the charge is transferred from the falling bit-lines to precharge the rising bit-lines while both the sender and the receiver are off. We simulate this 8-bit charge recovery bus with data based on realistic benchmarks. The power savings average 20% over typical on-chip and off-chip bus capacitances. The savings increase with larger bus capacitances and longer shorting times. The overhead of the control circuitry is estimated at 3.6% of the total power consumption.
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U2 - 10.1109/ASIC.2000.880750
DO - 10.1109/ASIC.2000.880750
M3 - Article
AN - SCOPUS:0033680915
SN - 1063-0988
SP - 283
EP - 287
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
ER -