TY - JOUR
T1 - Design of energy-efficient circuits and systems using tunnel field effect transistors
AU - Mukundrajan, Ravindhiran
AU - Cotter, Matthew
AU - Bae, Sungmin
AU - Saripalli, Vinay
AU - Irwin, Mary Jane
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - Energy efficiency is considered to be the most critical design parameter for ubiquitous and mobile computing systems. With consumers expecting improved functionality and performance from these systems without compromising on battery life, there is urgent need to explore emerging technologies that can overcome the limitations of CMOS and deliver greater energy efficiency. The potential of one such prospective metal oxide semiconductor field effect transistor replacement device, the tunnel FET (TFET), is evaluated in this study. Novel circuit designs are presented to overcome unique design challenges posed by TFETs. Further, the impact of TFETs at different levels of design abstraction is characterised by evaluating a novel sparse prefix tree adder and a field programmable gate array. A considerable improvement in delay and significant reduction in energy is observed because of the combined impact of circuit and technology co-exploration.
AB - Energy efficiency is considered to be the most critical design parameter for ubiquitous and mobile computing systems. With consumers expecting improved functionality and performance from these systems without compromising on battery life, there is urgent need to explore emerging technologies that can overcome the limitations of CMOS and deliver greater energy efficiency. The potential of one such prospective metal oxide semiconductor field effect transistor replacement device, the tunnel FET (TFET), is evaluated in this study. Novel circuit designs are presented to overcome unique design challenges posed by TFETs. Further, the impact of TFETs at different levels of design abstraction is characterised by evaluating a novel sparse prefix tree adder and a field programmable gate array. A considerable improvement in delay and significant reduction in energy is observed because of the combined impact of circuit and technology co-exploration.
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U2 - 10.1049/iet-cds.2012.0387
DO - 10.1049/iet-cds.2012.0387
M3 - Article
AN - SCOPUS:84884303823
SN - 1751-858X
VL - 7
SP - 294
EP - 303
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 5
ER -