Design of residue number system arithmetic units for a VLSI adaptive equalizer

Inseop Lee; W. Kenneth Jenkins

doi:10.1109/GLSV.1998.665222

Design of residue number system arithmetic units for a VLSI adaptive equalizer

Inseop Lee, W. Kenneth Jenkins

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and an update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper.

Original language	English (US)
Title of host publication	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publisher	IEEE Comp Soc
Pages	179-184
Number of pages	6
ISBN (Print)	0818684097
DOIs	https://doi.org/10.1109/GLSV.1998.665222
State	Published - 1998
Event	Proceedings of the 1998 8th Great Lakes Symposium on VLSI - Lafayette, LA, USA Duration: Feb 19 1998 → Feb 21 1998

Other

Other	Proceedings of the 1998 8th Great Lakes Symposium on VLSI
City	Lafayette, LA, USA
Period	2/19/98 → 2/21/98

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/GLSV.1998.665222

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title = "Design of residue number system arithmetic units for a VLSI adaptive equalizer",

abstract = "This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and an update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper.",

author = "Inseop Lee and Jenkins, {W. Kenneth}",

year = "1998",

doi = "10.1109/GLSV.1998.665222",

language = "English (US)",

isbn = "0818684097",

pages = "179--184",

booktitle = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

publisher = "IEEE Comp Soc",

note = "Proceedings of the 1998 8th Great Lakes Symposium on VLSI ; Conference date: 19-02-1998 Through 21-02-1998",

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AU - Jenkins, W. Kenneth

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N2 - This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and an update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper.

AB - This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and an update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper.

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BT - Proceedings of the IEEE Great Lakes Symposium on VLSI

PB - IEEE Comp Soc

T2 - Proceedings of the 1998 8th Great Lakes Symposium on VLSI

Y2 - 19 February 1998 through 21 February 1998

ER -

Design of residue number system arithmetic units for a VLSI adaptive equalizer

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