Design of temperature resilient clock distribution network for 3D ICs :Tutorial: High density high performance package and 2.5D/3D interconnect design

Madhavan Swaminathan; Sung Joo Park; Nitish Natu

Design of temperature resilient clock distribution network for 3D ICs :Tutorial: High density high performance package and 2.5D/3D interconnect design

Madhavan Swaminathan, Sung Joo Park, Nitish Natu

Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

Energy Efficiency will be a MAJOR driver in the future Temperature and Power Supply Noise effects become dominant in such scenarios 3D Integration poses unique problems in both these areas CLOCK DISTRIBUTION NETWORK in 3D ICs is one example SKEW due to TEMPERATURE GRADIENTS is a big problem Two compensation methods discussed Adaptive Voltage Tunable Delay Skew Vs Temperature and Compensation methods validated through FPGA Using Custom IC (instead of FPGA) results in manageable overheads in power and area while providing significant improvement in Skew compensation Working on the tapeout of the Custom IC.

Original language	English (US)
State	Published - 2014
Event	DesignCon 2014: Where the Chip Meets the Board - Santa Clara, CA, United States Duration: Jan 28 2014 → Jan 31 2014

Conference

Conference	DesignCon 2014: Where the Chip Meets the Board
Country/Territory	United States
City	Santa Clara, CA
Period	1/28/14 → 1/31/14

All Science Journal Classification (ASJC) codes

Computer Graphics and Computer-Aided Design
Human-Computer Interaction

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Cite this

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title = "Design of temperature resilient clock distribution network for 3D ICs :Tutorial: High density high performance package and 2.5D/3D interconnect design",

abstract = "Energy Efficiency will be a MAJOR driver in the future Temperature and Power Supply Noise effects become dominant in such scenarios 3D Integration poses unique problems in both these areas CLOCK DISTRIBUTION NETWORK in 3D ICs is one example SKEW due to TEMPERATURE GRADIENTS is a big problem Two compensation methods discussed Adaptive Voltage Tunable Delay Skew Vs Temperature and Compensation methods validated through FPGA Using Custom IC (instead of FPGA) results in manageable overheads in power and area while providing significant improvement in Skew compensation Working on the tapeout of the Custom IC.",

author = "Madhavan Swaminathan and Park, {Sung Joo} and Nitish Natu",

year = "2014",

language = "English (US)",

note = "DesignCon 2014: Where the Chip Meets the Board ; Conference date: 28-01-2014 Through 31-01-2014",

}

Design of temperature resilient clock distribution network for 3D ICs :Tutorial: High density high performance package and 2.5D/3D interconnect design. / Swaminathan, Madhavan; Park, Sung Joo; Natu, Nitish.
2014. Paper presented at DesignCon 2014: Where the Chip Meets the Board, Santa Clara, CA, United States.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Design of temperature resilient clock distribution network for 3D ICs :Tutorial

T2 - DesignCon 2014: Where the Chip Meets the Board

AU - Swaminathan, Madhavan

AU - Park, Sung Joo

AU - Natu, Nitish

PY - 2014

Y1 - 2014

N2 - Energy Efficiency will be a MAJOR driver in the future Temperature and Power Supply Noise effects become dominant in such scenarios 3D Integration poses unique problems in both these areas CLOCK DISTRIBUTION NETWORK in 3D ICs is one example SKEW due to TEMPERATURE GRADIENTS is a big problem Two compensation methods discussed Adaptive Voltage Tunable Delay Skew Vs Temperature and Compensation methods validated through FPGA Using Custom IC (instead of FPGA) results in manageable overheads in power and area while providing significant improvement in Skew compensation Working on the tapeout of the Custom IC.

AB - Energy Efficiency will be a MAJOR driver in the future Temperature and Power Supply Noise effects become dominant in such scenarios 3D Integration poses unique problems in both these areas CLOCK DISTRIBUTION NETWORK in 3D ICs is one example SKEW due to TEMPERATURE GRADIENTS is a big problem Two compensation methods discussed Adaptive Voltage Tunable Delay Skew Vs Temperature and Compensation methods validated through FPGA Using Custom IC (instead of FPGA) results in manageable overheads in power and area while providing significant improvement in Skew compensation Working on the tapeout of the Custom IC.

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M3 - Paper

AN - SCOPUS:84904121362

Y2 - 28 January 2014 through 31 January 2014

ER -

Design of temperature resilient clock distribution network for 3D ICs :Tutorial: High density high performance package and 2.5D/3D interconnect design

Abstract

Conference

All Science Journal Classification (ASJC) codes

UN SDGs

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