Design tradeoffs in high speed multipliers and FIR filters

Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


In this paper, we study the effects of modified Booth recoding, pipeline granularity and clocking on the speed, power dissipation and transistor count of different types of multipliers and FIR filters. Detailed simulations show that recoding may not always result in an improvement in delay. We propose a way of reducing the activity factor of a Booth multiplier by guarded evaluation. As systems become faster and faster, we can see the trend shifting from pipelining at the level of blocks of bits to bit-level, half-bit-level and even gate-level pipelining. We run detailed experiments to answer the question of how fine-grain can the depth of pipelining in high-throughput multipliers and filters be made before the increase in power consumption overpowers the speed gain. It is our observation that gate-level pipelining increases power dissipation without improving the speed significantly when compared to half-bit level pipelining.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Number of pages4
StatePublished - 1996
EventProceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India
Duration: Jan 3 1996Jan 6 1996


OtherProceedings of the 1996 9th International Conference on VLSI Design
CityBangalore, India

All Science Journal Classification (ASJC) codes

  • General Engineering


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