TY - JOUR
T1 - Designing a 3-D FPGA
T2 - Switch box architecture and thermal issues
AU - Gayasen, Aman
AU - Narayanan, Vijaykrishnan
AU - Kandemir, Mahmut
AU - Rahman, Arifur
N1 - Funding Information:
Manuscript received November 10, 2006; revised March 26, 2007. This work was supported in part by the National Science Foundation under NSF CAREER 0093085, NSF CCF 0702617, and by a grant from MARCO/GSRC. A. Gayasen is with R&D Department, Synopsys, Sunnyvale, CA 94043 USA (e-mail: [email protected]). N. Vijaykrishnan is with the Departments of Computer Science and Engineering and Electrical Engineering, Pennsylvania State University, University Park, PA 16802 USA. M. Kandemir is with the Computer Science and Engineering Department, Pennsylvania State University, University Park, PA 16802 USA. A. Rahman is with Xilinx Research Laboratories, San Jose, CA 95124 USA. Digital Object Identifier 10.1109/TVLSI.2008.2000456
PY - 2008/7
Y1 - 2008/7
N2 - Three-dimensional (3-D) integration is an attractive technology to reduce wirelengths in a field-programmable gate array (FPGA). However, it suffers from two problems: one, the inter-layer vias are limited in number, and second, the increased power density leads to high junction temperatures. In this paper, we tackle the first problem by designing switch boxes that maximize the use of the vias. Compared to the previously used subset switch box, our best switch box reduces the number of vias by about 49% and area-delay product by about 9%. For the second problem, we utilize the difference in power densities between CLBs and some of the hard blocks in modern FPGAs to distribute the power more uniformly across the FPGA. The peak temperature in a two-layer FPGA reduces by about 16°C after our change.
AB - Three-dimensional (3-D) integration is an attractive technology to reduce wirelengths in a field-programmable gate array (FPGA). However, it suffers from two problems: one, the inter-layer vias are limited in number, and second, the increased power density leads to high junction temperatures. In this paper, we tackle the first problem by designing switch boxes that maximize the use of the vias. Compared to the previously used subset switch box, our best switch box reduces the number of vias by about 49% and area-delay product by about 9%. For the second problem, we utilize the difference in power densities between CLBs and some of the hard blocks in modern FPGAs to distribute the power more uniformly across the FPGA. The peak temperature in a two-layer FPGA reduces by about 16°C after our change.
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U2 - 10.1109/TVLSI.2008.2000456
DO - 10.1109/TVLSI.2008.2000456
M3 - Article
AN - SCOPUS:48149113121
SN - 1063-8210
VL - 16
SP - 882
EP - 893
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
M1 - 4539804
ER -