Abstract
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. Hence, the design of leakage-conscious memory and data path components is vital. This paper focuses on designing a 32-bit double precision multiplier, and snows haw the appropriate choice of implementation primitives used in the design can provide significant leakage energy savings without much impact on performance.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 654-657 |
| Number of pages | 4 |
| Journal | Proceedings of the IEEE International Conference on VLSI Design |
| Volume | 17 |
| State | Published - 2004 |
| Event | Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India Duration: Jan 5 2004 → Jan 9 2004 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
