Determining worst-case eye height in low BER channels using Bayesian optimization

Majid Ahadi Dolatsara, Madhavan Swaminathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Eye diagram simulation and bit error rate (BER) estimation is an essential task in signal integrity. A lengthy time domain simulation is required for non-LTI systems where statistical methods are generally inaccurate. However, with the BER reaching less than 10-12, and with exponential increase in bandwidth, this task is expected to become more challenging and exorbitantly time consuming. In particular, the concern is with inter-symbol interference (ISI) effect, which can be caused by the state of several earlier bits. Therefore, this paper suggests an optimization method to find the bit patterns causing the lowest received high symbol, and the highest received low symbol, at the sampling time point. Difference of these values can be used to estimate the worst-case eye height. The proposed approach is based on a mapping method and Bayesian optimization, which provides a significant speedup compared to the traditional transient eye. This optimization technique is capable of solving both non-linear and non-convex problems. A numerical example is provided to show performance of the proposed approach.

Original languageEnglish (US)
Title of host publication2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728134277
DOIs
StatePublished - Feb 2020
Event11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica
Duration: Feb 25 2020Feb 28 2020

Publication series

Name2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conference

Conference11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Country/TerritoryCosta Rica
CitySan Jose
Period2/25/202/28/20

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation

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