In this paper, we explore the design space of two possible candidate FETs for sub-10-nm technologies-FinFET like double gate MOSFETs (DGFETs) and Schottky-barrier (SB) devices. Though SB devices are expected to have lower ON current, their lower source/drain resistance (RS/D) can be important in scaled technologies. We evaluate the suitability of the optimized devices for logic and memory designs in the sub-10-nm technologies using a comparative device-circuit analysis based on nonequilibrium Green's function-based transport models and HSPICE circuit simulation. The devices are optimized with gate-to-source (S)/drain (D) underlap, and proper body thickness to suppress direct source-to-drain tunneling (DSDT). Our analysis shows that introduction of gate-to-S/D underlap provides the benefit of reducing DSDT, while reduced body thickness provides a tradeoff between low DSDT and high RS/D. Results also show that DGFETs provide higher drive strength even with larger RS/D. As a result, DGFET-based logic shows higher performance, and better read stability for memory while SBFET-based memory shows higher write stability.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering