TY - GEN
T1 - Device circuit Co design of FEFET based logic for low voltage processors
AU - George, Sumitha
AU - Aziz, Ahmedullah
AU - Li, Xueqing
AU - Kim, Moon Seok
AU - Datta, Suman
AU - Sampson, John
AU - Gupta, Sumeet
AU - Narayanan, Vijaykrishnan
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/9/2
Y1 - 2016/9/2
N2 - Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at VDD.
AB - Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at VDD.
UR - https://www.scopus.com/pages/publications/84988983699
UR - https://www.scopus.com/pages/publications/84988983699#tab=citedBy
U2 - 10.1109/ISVLSI.2016.116
DO - 10.1109/ISVLSI.2016.116
M3 - Conference contribution
AN - SCOPUS:84988983699
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 649
EP - 654
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
PB - IEEE Computer Society
T2 - 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Y2 - 11 July 2016 through 13 July 2016
ER -