Device-circuit co-optimization for robust design of FinFET-Based SRAMs

A set of device-circuit co-design techniques oriented to increase the resilience of FinFET SRAMs circuits is presented in a study. Co-optimization of fin ratio, thickness, orientation, and height are investigated and its impact on performance and area evaluated. The study presents techniques which use a device-circuit co-design approach to achieve enhancement in stability of SRAM cells. These techniques lead to the mitigation of the design conflicts in SRAMs and make them more robust toward process variations. It is shown that new device structures and design methodologies can be developed by utilizing unique features of FinFETs, and that these devices are especially suitable for memories. It is essential to observe conflicting design requirements for the strength of the access transistors to simultaneously achieve large read stability and write ability.