Device design for gate-all-around-nanowire tunneling CMOS-FETs of Axial Ge-Si heterojunction through Inverter Performance Evaluation

The realistic performance of gate-all-around (GAA) nanowire (NW) tunneling-FETs (tFET) is evaluated through mixed-mode device/circuit simulation of CMOS inverters. The novel features of device design include using Ge-Si source/channel heterojunction (HJ) in axial direction of NW to achieve high on-current; lightly-doped drain-extension and gate underlap to suppress ambipolarity in transfer characteristics of tFETs. Both p- and n-tFETs are optimized through selection of channel/ drain materials (Si for n- and Ge for p-type). The inverter circuit performance is evaluated with these complementary NW-tFETs as constructed without relying on any simplification in compact modeling, thus making it easy to assess the impact of device structural parameters. Simulation shows excellent switching behavior of inverters at Vdd = 0.5 V with less sensitivity to temperature change.