TY - GEN
T1 - Device/circuit interactions at 22nm technology node
AU - Roy, Kaushik
AU - Kulkarni, Jaydeep P.
AU - Gupta, Sumeet Kumar
PY - 2009/1/1
Y1 - 2009/1/1
N2 - As transition is being made into 22nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss the challenges of device-circuit-system design at the 22 nm node and present techniques at different levels of design abstraction to meet these challenges. In particular, we discuss different device options for multi-gate FETs. Logic and memory design using multi-gate FETs is also considered. Finally, we briefly discuss process variation tolerant system design methodologies for such scaled technologies.
AB - As transition is being made into 22nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss the challenges of device-circuit-system design at the 22 nm node and present techniques at different levels of design abstraction to meet these challenges. In particular, we discuss different device options for multi-gate FETs. Logic and memory design using multi-gate FETs is also considered. Finally, we briefly discuss process variation tolerant system design methodologies for such scaled technologies.
UR - http://www.scopus.com/inward/record.url?scp=70350724694&partnerID=8YFLogxK
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U2 - 10.1145/1629911.1629942
DO - 10.1145/1629911.1629942
M3 - Conference contribution
AN - SCOPUS:70350724694
SN - 9781605584973
T3 - Proceedings - Design Automation Conference
SP - 97
EP - 102
BT - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Y2 - 26 July 2009 through 31 July 2009
ER -